1. Field of the Invention
The present invention relates to the correction of the offset of an amplification chain, and in particular of the offset of an amplification and low-pass filtering chain.
2. Description of the Related Art
An amplification and filtering chain is for example used at the output of an antenna block of a mobile phone to amplify and filter a noisy signal received with a low amplitude. Amplifiers used in such a chain frequently exhibit an offset to which the signals received by the amplifiers add. This offset reduces the maximum value of the signals that can be received by the amplifiers without for the amplifiers to be saturated, which reduces the chain performances. The offset of an amplification chain is generally corrected by subtracting from the signal received at the chain input a correction signal substantially equal to the chain offset.
FIG. 1 very schematically shows an amplification and filtering chain 2 provided with an offset correction circuit 4. Chain 2 and correction circuit 4 are integrated on a same chip. Chain 2 comprises an input terminal I receiving a signal from an antenna block not shown and an output terminal O. Terminal I is connected to the input of an amplifier 6. The output of amplifier 6 is filtered by a low-pass filter 8 having a cut-off frequency Fc8 before being provided to an amplifier 10. The output of amplifier 10 is filtered by a low-pass filter 12 having a cut-off frequency Fc12 before being provided to output terminal O. Correction circuit 4 comprises a digital automaton 14 having an input terminal connected to output terminal O of the chain. Automaton 14 provides over a bus 16 a control word COM to a digital-to-analog converter (DAC) 18. The output of converter 18 is connected to input terminal I of chain 2. Correction circuit 4 further comprises a switch 20 enabling cancellation of the signal provided by the antenna block to input terminal I. Automaton 14 and switch 20 are controlled by a means not shown.
It is considered hereafter that terminal I receives from the antenna block an input signal SI and signals at higher frequency, and that terminal O provides as a response an output signal SO. If the signals at higher frequency are totally suppressed by the filters of chain 2; if G is the gain of chain 2 and Δ is the offset of chain 2; and if δ is a correction signal, positive or negative, permanently provided on input terminal I by converter 18 as a response to word COM, one has, in normal operation of the chain: SO=G.(Δ+δ+SI).
The value of correction signal δ is determined in a setting phase to minimize sum Δ+δ. In the setting phase, switch 20 is off. Output O then provides an output signal SO=G(Δ+δ). At the beginning of the setting phase, automaton 14 provides a control word COM such that converter 18 generates a zero correction signal 6, after which it measures the sign of signal SO. Automaton 14 then modifies the value of word COM to any one of two consecutive values between which signal SO=G(Δ+δ) switches sign. This value of word COM, for which sum Δ+δ is minimum, is then memorized and permanently provided to converter 18. The setting phase is over, switch 20 is on, and the chain can operate normally. According to an alternative, the automaton may at the beginning of the setting phase provide a control word COM for which it is provided that sum Δ+δ is zero, then adjust the value of signal δ.
The above correction circuit operates satisfactorily but it requires a setting phase which may be too long. Indeed, in certain systems such as mobile phones, signal SI is received in the form of packets separated by idle periods. To limit the system consumption, amplification chain 2 is only activated to receive each packet and powered off for idle periods. Now, the offset of amplification chain 2 may vary from one activation of the chain to the other, for example, due to a change in temperature or in supply voltage. Thus, the setting phase of the offset correction circuit may be implemented after each activation of chain 2. The longer the setting phase, the longer chain 2 must be powered on before the packet reception, which increases the system consumption.
It has been seen that the setting of correction circuit 4 comprises a modification of the bits of word COM by digital automaton 14. Each time digital automaton 14 modifies a bit of word COM, and thereby signal δprovided at the chain input, it must wait for a predetermined duration t to be sure that the chain has effectively transmitted the modification to its output SO before measuring the sign of signal SO. In practice, if the chain exhibits a cut-off frequency Fc (the smallest of cut-off frequencies Fc8 and Fc12 of filters 8 and 12), predetermined duration t depends on 1/Fc. If word COM comprises n bits, the setting phase lasts for n times duration t. To reduce the duration of the setting phase, the number of bits of word COM thus has to be reduced, which reduces the accuracy of offset Δ.
A solution to this problem consists of not using the above correction circuit 4, and of using an analog correction circuit which requires no setting phase and subtracts from signal SI the D.C. portion of a feedback signal equal to the division of output signal SO by gain G of the chain. However, such a correction circuit is expensive since it imposes using a large capacitor to extract the D.C. portion of the feedback signal.